A digital twin is a virtual representation that accurately replicates its physical counterpart, fostering bi-directional real-time data exchange throughout the entire process lifecycle. This study explores the integration of digital twins into additive manufacturing processes. Here, digital twins help to control the residual stress design in build parts. Employing faster-than-real-time and highly accurate surrogate models enables the prediction of altered structural properties, facilitating on-the-fly re-optimizing the ongoing manufacturing process to achieve desired structural outcomes. Consequently, this approach contributes significantly to realizing the first-time-right paradigm in additive manufacturing. The foundation of successful digital twin derivation lies in the physics-based modeling of the additive manufacturing process. Predicting final structural properties necessitates mapping input parameters to potentially non-linear part properties. However, a challenge arises from the need to provide faster-than-real-time replications of these mappings through simulations, particularly as the complexity and computational cost of multi-physical simulation models increase. This study addresses the challenge above by presenting an efficient reduced order modeling methodology for digital twins, utilizing autoencoders for spatial compression and neural ODEs for latent space system dynamics identification, ensuring low test errors of the twin when applied to pertinent test data. The proposed solution “TwinLab” [2] includes a comprehensive software suite that automates simulation model management, training data selection, reduced-order model derivation, and integrating digital-twin-based control techniques into a unified framework. The versatility of this framework, specifically designed for seamless integration with various simulation models, was initially exemplified through its application in autonomous thermal food processing [1,2]. Computational efficiency is demonstrated by characteristic solution times of one-half of a second, imposing negligible processing costs on a single-core processor.